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[Craftor Original] EZ

In the case of

sync folders between usb and pcDisclaimer: Craftor original, reproduced please indicate the source.

In the case of

Using the chip: CY7C68013A (Cypress) and XC3S50AN (Xilinx)

In the case of

First, the schematic diagram

The FPGA and EZ-USB are connected via an asynchronous FIFO. The following screenshots are from the Cypress manual EZ-USB_TRM.pdf.

The signals in Figures 9-19 and 9-22 are merged together and connected to the FPGA.

The following signals are used in this example: FIFOADR [7: 0] (only 8-bit bus), SLRD, SLOE, SLWR, FLAGA (configured as EP6 FULL), FLAGB (configured as EP2 EMPTY), PKTEND (constant 1) , SLCS # (constant 0)

In the case of

Second, FPGA read and write SlaveFIFO timing

Asynchronous write, when FULL is not 0, SLWR falling edge of the time will write the data on the bus, keep a cycle to write data.

Asynchronous read, when EMPTY is not 0, SLOE and move files software SLRD will be pulled low, read the number on the bus for half a cycle.

In the case of

-> There are schematic diagrams in the annex

In the case of

Third, FPGA code

The engineering structure is shown in the following figure in Xilinx ISE.

1) usb_bmd.v for the top test file, test the uplink and downlink data.

2) RX_FIFO is the downstream data cache FIFO, and TX_FIFO is the upstream data cache FIFO.

The project directly in the FPGA internal FIFO, according to the actual situation to increase or decrease the FIFO, the minimum depth of not less than 512.

3) usb_trx FPGA and CY7C68013A communication core module, including: rx_engine.v downlink interface, tx_engine uplink interface, clk_div.v frequency module (control FPGA read and write SlaveFIFO frequency, no more than 48M).

Can be adjusted according to the actual circuit or reduce the frequency factor, but is not recommended to modify the source code in the frequency factor has been measured for the best case, double panel does not do any impedance matching case, you can stabilize the transmission of data. If the PCB impedance to do better, but also appropriate to try to increase.

4) S3an.ucf for the pin constraint file, but also according to their own FPGA pins to modify.

In the case of

- There are Verilog source code in the attachment

In the case of

Second, the firmware program, see Annex CFR-FIFO-1.1.iic

Download via CyConsole to an external EEPROM (see how to download in Study Notes [1]).

The firmware uses the asynchronous SlaveFIFO mode, using the endpoint EP2 and EP6, 512B size, 4x buffer.

- u0026 gt; The firmware is for learning only, the source code is not public and does not need to be public.

In the case of

Third, the test

1) Use EZ-USB CyConsole, select Endpoint 6 IN, and receive the number from 00 to FF.

Because in the usb_bmd.v code, continue to TX_FIFO write 8-bit cnt, starting from 0. As shown below

2) Use the CyBulkLoop program to perform closed-loop testing. Packet length of 512, from 0 to accumulate, the test results as shown below.

Careful readers can find that the actual usb_bmd code in the hands and feet, upload the data is not really issued data, but their upload 00 ~ FF.

Because if the code in the RX and TX closed loop, is a downlink data (8b) immediately upload a data. While the USB SlaveFIFO is 512B, each time the uplink data is 512B minimum, and must be an integer multiple of 512B. In the practical application of attention.

annex:

http://dl.dbank.com/c04h9fkkbu




About the Author

Cyrus

My name is Cyrus and I am studying Art and Art at Waddinxveen / Netherlands.


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